A time division multiplexer converts input data bits into a serialized data output. The multiplexer receives a clock signal at a selector input of the multiplexer that causes the multiplexer to alternately select among the data bits and successively output the selected bits in the serialized data. Circuit delays introduced by the multiplexer and associated clock circuits can cause an undesired phase-misalignment between the clock and the input data that is selected by the clock. The phase-misalignment can cause indeterminate data selection in the multiplexer, which results in bit errors in the serialized data. The phase-misalignment is especially problematic in a multiplexer that operates in the gigabit frequency range.